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publication number s71pl-j_00 revision b amendment 6 issue date february 17, 2010 s71pl-j based mcps s71pl-j based mcps cover sheet data sheet (retired product) this product has been retired and is not recommended for new designs. for new designs, s71gl-a or s71gl-n supersedes s71pl-j. please contact your local spansion sales office to determine the appropriate migration device, specifications, and ordering information. availability of this document is retained for reference and historical purposes only.
2 s71pl-j based mcps s71pl-j_00_b6 february 17, 2010 data sheet (retired product)
publication number s71pl-j_00 revision b amendment 6 issue date february 17, 2010 note: this product has been retired and is not recommended for new designs. for new designs, s71gl-a or s71gl-n supersedes s71pl-j. please contact your local spansion sales office to determi ne the appropriate migration device, specifications, and ordering information. availability of this document is retained for reference and historical purposes only. features ? power supply voltage of 2.7 v to 3.1 v ? high performance ? 65 ns (65 ns flash, 70 ns psram) ? packages ? 7 x 9 x 1.2 mm 56 ball fbga ? 8 x 11.6 x 1.2 mm 64 ball fbga ? 8 x 11.6 x 1.4 mm 84 ball fbga ? operating temperature ? ?25c to +85c ? ?40c to +85c general description the s71pl series is a product line of stacked mu lti-chip product (mcp) packages and consists of: ? one or more s29pl (simultaneous read/write) flash memory die ? psram or sram the 256 mb flash memory consists of two s29pl127j devices. in this case, ce#f2 is used to access the second flash and no extra address lines are required. the products covered by this document are listed in the table below: notes 1. not recommended for new designs; contact your local spansion sales representative for details. 2. not recommended for new designs: use s71pl127n and s71pl256n instead. s71pl-j based mcps stacked multi-chip produc t (mcp) flash memory and ram 256m/128/64/32 megabit (16/8/4/2m x 16-bit) cmos 3.0 volt-only simultaneous operation pa ge mode flash memory and 64/32/16/8/4 megabit (4m/2m /1m/512k/256k x 16-bit) static ram/psram data sheet flash memory density 32mb (1) 64mb (1) 128mb (2) 256mb (2) psram density 4 mb s71pl032j40 8 mb s71pl032j80 s71pl064j80 16 mb s71pl032ja0 s71pl064ja0 32 mb s71pl064jb0 s71pl127jb0 64 mb s71pl127jc0 s71pl254jc0 flash memory density 32mb 64mb sram density (1) 4 mb S71PL032J04 8 mb s71pl032j08 s71pl064j08 16 mb s71pl064j0a
4 s71pl-j based mcps s71pl-j_00_b6 february 17, 2010 data sheet for detailed specifications, please refer to the in dividual data sheets listed in the following table. note none of these ram specifications are applicable for new designs . please contact your local spansion sales representative for de tails. document publication identification number (pid) s29pl-j s29pl-j_m0 psram type 1 psram_12 psram type 2 psram_15 8 mb psram type 3 psram_25 16 mb psram type 3 psram_06 psram type 4 psram_18 psram type 5 psram_21 psram type 6 psram_14 psram type 7 psram_13 4 mb/8 mb sram type 1 sram_02 16 mb sram type 1 sram_06 sram type 4 sram_07 32 mb psram type 8 psram_31
february 17, 2010 s71pl-j_00_b6 s71pl-j based mcps 5 data sheet 1. product selector guide 1.1 32 mb flash memory 1.2 64 mb flash memory 1.3 128 mb flash memory not recommended for new designs; use s71pl127n instead. 1.4 256mb flash memo ry (2xs29pl127j) not recommended for new designs: use s71pl256n instead. device-model# flash access time (ns) (p)sram density (p)sram access time (ns) psram type package S71PL032J04-0b 65 4m sram 70 sram1 tsc056 S71PL032J04-0k 65 4m sram 70 sram4 tsc056 s71pl032j40-0k 65 4m psram 70 psram4 tlc056 s71pl032j08-0b 65 8m sram 70 sram1 tsc056 s71pl032j80-0f 65 8m psram 70 psram5 tsc056 s71pl032j80-q7 65 8m psram 70 psram1 tsc056 s71pl032j80-qf 65 8m psram 70 psram3 tsc056 s71pl032ja0-0k 65 16 mb psram 70 psram1 tsc056 s71pl032ja0-qf 65 16 mb psram 70 psram3 tsc056 s71pl032ja0-0z 65 16m psram 70 psram7 tlc056 device-model# flash access time (ns) (p)sram density (p)sram access time (ns) (p)sram type package s71pl064j80-07 65 8m psram 70 psram4 tsc056 s71pl064j0a-0s 65 16m sram 70 sram 4 tlc056 s71pl064ja0-0z 65 16m psram 70 psram7 tlc056 s71pl064ja0-0b 65 16m psram 70 psram3 tlc056 s71pl064ja0-07 65 16m psram 70 psram1 tlc056 s71pl064ja0-0p 65 16m psram 70 psram7 tlc056 s71pl064jb0-qb 65 32m psram 70 psram2 tlc056 s71pl064jb0-0u 65 32m psram 70 psram8 tlc056 device-model# flash access time (ns) psram density psram access time (ns) psram type package s71pl127jb0-9z 65 32m psram 70 psram7 tla064 s71pl127jb0-9u 65 32m psram 70 psram6 tla064 s71pl127jb0-9b 65 32m psram 70 psram2 tla064 s71pl127jc0-9b 65 64m psram 70 psram2 tla064 s71pl127jc0-9z 65 64m psram 70 psram7 tla064 s71pl127jc0-9u 65 64m psram 70 psram6 tla064 device-model# flash access time (ns) psram density psram access time (ns) psram type package s71pl254jc0-tb 65 64m psram 70 psram2 fta084 s71pl254jc0-tz 65 64m psram 70 psram7 fta084
6 s71pl-j based mcps s71pl-j_00_b6 february 17, 2010 data sheet 2. mcp block diagram notes 1. for 1 flash + psram, ce#f1=ce#. for 2 flash + psram, ce#=ce#f1 and ce#f2 is the chip-enable for the second flash. 2. for 256mb only, flash 1 = flash 2 = s29pl127j. v ss reset# flash 1 io 15 -io 0 v cc f dq 15 to dq 0 ry/by# wp#/acc v cc v cc ce#f1 flash-only address shared address oe# we# flash 2 (note 2) ce#f2 (note 1) v ccs v cc ce#s ub#s lb#s ce# ub# lb# psram/sram ce2
february 17, 2010 s71pl-j_00_b6 s71pl-j based mcps 7 data sheet 3. connection diagrams figure 3.1 s71pl032j connection diagram notes 1. may be shared depending on density. ? a19 is shared for the 16m psram configuration. ? a18 is shared for the 8m psram and above configurations. 2. connecting all v cc and v ss balls to v cc and v ss is recommended. mcp flash-only addresses shared addresses s71pl032ja0 a20 a19-a0 s71pl032j80 a20-a19 a18-a0 s71pl032j08 a20-a19 a18-a0 s71pl032j40 a20-a18 a17-a0 S71PL032J04 a20-a18 a17-a0 c3 ub# d3 a18 e3 a17 f3 dq1 g3 dq9 h3 dq10 dq2 b3 lb# c5 ce2s a20 g5 dq4 h5 vccs rfu b5 we# c6 a19 d6 a9 e6 a10 f6 dq6 g6 dq13 h6 dq12 dq5 b6 a8 c4 rst#f ry/by# g4 dq3 h4 vccf dq11 b4 wp/acc c7 a12 d7 a13 e7 a14 f7 rfu g7 dq15 h7 dq7 dq14 b7 a11 c8 a15 d8 rfu e8 rfu f8 a16 g8 rfu vss c2 a6 d2 a5 e2 a4 f2 vss g2 oe# h2 dq0 ce1#s dq8 b2 a7 c1 a3 d1 a2 e1 a1 f1 a0 g1 ce1#f f5 f4 b1 b8 a3 a5 a6 a4 a7 a2 ram only shared (note 1) flash only legend reserved fo r future use 56-ball fine-pitch ball grid array (top view, balls facing down)
8 s71pl-j based mcps s71pl-j_00_b6 february 17, 2010 data sheet figure 3.2 s71pl064j connection diagram notes 1. may be shared depending on density. ? a20 is shared for the 32m psram configuration. ? a19 is shared for the 16m psram and above configurations. ? a18 is shared for the 8m psram and above configurations. 2. connecting all v cc and v ss balls to v cc and v ss is recommended. mcp flash-only addresses shared addresses s71pl064jb0 a21 a20-a0 s71pl064ja0 a21-a20 a19-a0 s71pl064j0a a21-a20 a19-a0 s71pl064j80 a21-a19 a18-a0 s71pl064j08 a21-a19 a18-a0 c3 ub# d3 a18 e3 a17 f3 dq1 g3 dq9 h3 dq10 dq2 b3 lb# c5 ce2s a20 g5 dq4 h5 vccs rfu b5 we# c6 a19 d6 a9 e6 a10 f6 dq6 g6 dq13 h6 dq12 dq5 b6 a8 c4 rst#f ry/by# g4 dq3 h4 vccf dq11 b4 wp/acc c7 a12 d7 a13 e7 a14 f7 rfu g7 dq15 h7 dq7 dq14 b7 a11 c8 a15 d8 a21 e8 rfu f8 a16 g8 rfu vss c2 a6 d2 a5 e2 a4 f2 vss g2 oe# h2 dq0 ce1#s dq8 b2 a7 c1 a3 d1 a2 e1 a1 f1 a0 g1 ce1#f f5 f4 b1 b8 a3 a5 a6 a4 a7 a2 ram only shared (note 1) flash only legend reserved fo r future use 56-ball fine-pitch ball grid array (top view, balls facing down)
february 17, 2010 s71pl-j_00_b6 s71pl-j based mcps 9 data sheet figure 3.3 s71pl127j connection diagram notes 1. may be shared depending on density. ? a21 is shared for the 64m psram configuration. ? a20 is shared for the 32m psram and above configurations. 2. a19 is shared for the 16m psram and above configurations 3. connecting all v cc and v ss balls to v cc & v ss is recommended. 4. ball l5 will be v cc f in the 84-ball density upgrades. do not connect to v ss or any other signal. mcp flash-only addresses shared addresses s71pl127jc0 a22 a21-a0 s71pl127jb0 a22-a21 a20-a0 e4 ub# f4 a18 g4 a17 h4 dq1 j4 dq9 k4 dq10 dq2 d 4 e 6 ce2s a20 j6 dq4 k6 vccs rfu d 6 rfu e7 a19 f7 a9 g7 a10 h7 dq6 j7 dq13 k7 dq12 dq5 d 7 e5 rst#f ry/by# j5 dq3 k5 vccf dq11 d5 rfu e8 a12 f8 a13 g8 a14 h8 rfu j8 dq15 k8 dq7 dq14 d8 e 9 f9 a21 g9 a22 h9 a16 j9 rfu vss e3 a6 f3 a5 g3 a4 h3 vss j3 oe# k3 dq0 ce1#s dq8 d3 e2 f2 a2 g2 a1 h2 a0 j2 ce#f h6 h5 b6 b5 ram only shared (note 1) flash only legend reserved fo r future use rfu rfu* l6 l5 lb# c 4 we# c6 a8 c7 wp/acc c5 a11 c8 a7 c3 a3 d2 a15 d9 a1 nc a10 nc m1 m10 nc nc *see notes below 64-ball fine-pitch ball grid array (top view, balls facing down)
10 s71pl-j based mcps s71pl-j_00_b6 february 17, 2010 data sheet figure 3.4 s71pl254j connection diagram notes 1. may be shared depending on density. ? a21 is shared for the 64m psram configuration. ? a20 is shared for the 32m psram configuration. 2. connecting all v cc & v ss balls to v cc & v ss is recommended. special handling instructions for fbga package special handling is required for flash memory products in fbga packages. flash memory devices in fbga packages may be damaged if exposed to ultrasonic cleaning methods. the package and/or data integrity may be compromised if t he package body is exposed to temperatures above 150 c for prolonged periods of time. mcp flash-only addresses shared addresses s71pl254jc0 a22 a21-a0 e4 ub# f4 a18 g4 a17 h4 dq1 j4 dq9 dq10 d4 e 6 ce2s a20 j6 dq4 vccs d6 e7 a19 f7 a9 g7 a10 h7 dq6 j7 dq13 dq12 d7 e5 rst#f ry/by# j5 dq3 vccf d5 e8 a12 f8 a13 g8 a14 h8 rfu j8 dq15 dq7 d8 e 9 f9 a21 g9 a22 h9 a16 j9 rfu vss e3 a6 f3 a5 g3 a4 h3 vss j3 oe# dq0 ce1#s d3 e2 f2 a2 g2 a1 h2 a0 j2 ce#f1 h6 h5 ram only shared (note 1) flash only legend reserved fo r future use a3 d2 a15 d9 a1 nc a10 nc m1 m10 nc nc c4 lb# we# c7 a8 wp/acc c8 a11 c9 rfu c3 a7 c2 rfu c6 c5 b4 rfu rfu b7 rfu ce#f2 b8 rfu b9 rfu b3 rfu b2 rfu b6 b5 l4 rfu rfu l7 rfu vccf l8 rfu l9 rfu l3 rfu l2 rfu l6 l5 k4 dq2 rfu k7 dq5 dq11 k8 dq14 k9 rfu k3 dq8 k2 rfu k6 k5 rfu rfu h6 h5 rfu rfu h6 h5 2nd flash only 84-ball fine-pitch ball grid array (top view, balls facing down)
february 17, 2010 s71pl-j_00_b6 s71pl-j based mcps 11 data sheet 4. pin description 5. logic symbol signal description a21?a0 22 address inputs (common) dq15?dq0 16 data inputs/outputs (common) ce1#f chip enable 1 (flash) ce#f2 chip enable 2 (flash) ce1#ps chip enable 1 (psram) ce2ps chip enable 2 (psram) oe# output enable (common) we# write enable (common) ry/by# ready/busy output (flash 1) ub# upper byte control (psram) lb# lower byte control (psram) reset# hardware reset pin, active low (flash 1) wp#/acc hardware write protect/acceleration pin (flash) v cc f flash 3.0 volt-only single power supply (see product sele ctor guide for speed options and voltage supply tolerances) v cc ps psram power supply v ss device ground (common) nc pin not connected internally 22 16 dq15?dq0 a21?a0 ce1#f oe# we # reset# r y/by# wp#/acc ub# ce2#f ce2ps ce1#ps lb#
12 s71pl-j based mcps s71pl-j_00_b6 february 17, 2010 data sheet 6. ordering information the order number is formed by a valid combinations of the following: 6.1 valid combinations valid combinations list configurations planned to be supported in volume for this device. consult your local sales office to confirm availability of specific valid combinations and to check on newly released combinations. s71pl 127 j b0 ba w 9 z 0 packing type 0=tray 2 = 7? tape and reel 3 = 13? tape and reel model number see the valid combinations table. package modifier 0 = 7 x 9 mm, 1.2 mm height, 56 balls (tlc056 or tsc065) 9 = 8 x 11.6 mm, 1.2 mm height, 64 balls (tla064 or tsb064) t = 8 x 11.6 mm, 1.4 mm height, 84 balls (fta084) q = see the valid combinations table temperature range w = wireless (-25 c to +85 c) package type ba = fine-pitch bga lead (pb)-free compliant package bf = fine-pitch bga lead (pb)-free package psram density c0 = 64 mb psram b0 = 32 mb psram a0 = 16 mb psram 80 = 8 mb psram 40 = 4 mb psram 0a = 16 mb psram 08 = 8 mb sram 04 = 4 mb sram process technology j = 110 nm, floating gate technology flash density 254= 256 mb 127= 128 mb 064= 64 mb 032= 32 mb product family s71pl multi-chip product (mcp)3.0-volt simultaneous read/write, page mode flash memory and ram
february 17, 2010 s71pl-j_00_b6 s71pl-j based mcps 13 data sheet notes 1. type 0 is standard. specify other options as required. 2. bga package marking omits leading ?s? and packing type designator from ordering part number. table 6.1 s71pl032j valid combinations base ordering part number package & temperature package modifier/ model number packing type speed options (ns) (p)sram type/ access time (ns) package marking S71PL032J04 baw 0b 0, 2, 3 (1) 65 sram2 / 70 (2) S71PL032J04 0k sram4 / 70 s71pl032j40 0k psram4 / 70 s71pl032j80 0f psram5 / 70 s71pl032j08 0b sram2 / 70 s71pl032j80 q7 psram1 / 70 s71pl032j80 qf psram3 / 70 s71pl032ja0 07 psram1 / 70 s71pl032ja0 qf psram3 / 70 s71pl032ja0 0z psram7 / 70 S71PL032J04 bfw 0b 0, 2, 3 (1) 65 sram2 / 70 (2) S71PL032J04 0k sram4 / 70 s71pl032j40 0k psram4 / 70 s71pl032j80 0f psram5 / 70 s71pl032j08 0b sram2 / 70 s71pl032j80 q7 psram1 / 70 s71pl032j80 qf psram3 / 70 s71pl032ja0 07 psram1 / 70 s71pl032ja0 qf psram3 / 70 s71pl032ja0 0z psram7 / 70 table 6.2 s71pl064j valid combinations base ordering part number package & temperature package modifier/ model number packing type speed options (ns) (p)sram type/ access time (ns) package marking s71pl064j80 baw 07 0, 2, 3 (1) 65 psram 4/70 (2) s71pl064j0a 0s sram1 / 70 s71pl064ja0 0b psram3 / 70 s71pl064ja0 07 psram1 / 70 s71pl064ja0 0p psram7 / 70 s71pl064jb0 qb psram2 / 70 s71pl064jb0 0u psram8 / 70 s71pl064j80 bfw 07 0, 2, 3 (1) 65 psram7 /70 (2) s71pl064j0a 0s sram1 / 70 s71pl064ja0 0b psram3 / 70 s71pl064ja0 07 psram1 / 70 s71pl064ja0 0p psram7 / 70 s71pl064jb0 qb psram2 / 70 s71pl064jb0 0u psram8 / 70
14 s71pl-j based mcps s71pl-j_00_b6 february 17, 2010 data sheet notes 1. type 0 is standard. specify other options as required. 2. bga package marking omits leading ?s? and packing type designator from ordering part number. notes 1. type 0 is standard. specify other options as required. 2. bga package marking omits leading ?s? and packing type designator from ordering part number. table 6.3 s71pl127j valid combinations base ordering part number package & temperature package modifier/ model number packing type speed options (ns) (p)sram type/ access time (ns) package marking s71pl127jb0 baw 9z 0, 2, 3 (1) 65 psram7 / 70 (2) s71pl127jb0 9u psram6 /70 s71pl127jc0 9b psram2 /70 s71pl127jc0 9z psram7 / 70 s71pl127jc0 9u psram6 / 70 s71pl127jb0 9b psram2 / 70 s71pl127jb0 bfw 9z 0, 2, 3 (1) 65 psram7 / 70 (2) s71pl127jb0 9u psram6 / 70 s71pl127jc0 9b psram2 /70 s71pl127jc0 9z psram7 / 70 s71pl127jc0 9u psram6 / 70 s71pl127jb0 9b psram2 / 70 table 6.4 s71pl254j valid combinations base ordering part number package & temperature model number packing type speed options (ns) (p)sram type/ access time (ns) package marking s71pl254jc0 baw tb 0, 2, 3 (1) 65 psram2 / 70 (2) s71pl254jc0 tz psram7 / 70 s71pl254jc0 bfw tb 0, 2, 3 (1) 65 psram2 / 70 (2) s71pl254jc0 tz psram7 / 70
february 17, 2010 s71pl-j_00_b6 s71pl-j based mcps 15 data sheet 7. physical dimensions tlc056?56-ball fine-pitch ball grid array (fbga) 9 x 7 mm package 3348 \ 16-038.22a package tlc 056 jedec n/a d x e 9.00 mm x 7.00 mm package symbol min nom max note a --- --- 1.20 profile a1 0.20 --- --- ball height a2 0.81 --- 0.97 body thickness d 9.00 bsc. body size e 7.00 bsc. body size d1 5.60 bsc. matrix footprint e1 5.60 bsc. matrix footprint md 8 matrix size d direction me 8 matrix size e direction n 56 ball count b 0.35 0.40 0.45 ball diameter ee 0.80 bsc. ball pitch ed 0.80 bsc ball pitch sd / se 0.40 bsc. solder ball placement a1,a8,d4,d5,e4,e5,h1,h8 depopulated solder balls notes: 1. dimensioning and tolerancing methods per asme y14.5m-1994. 2. all dimensions are in millimeters. 3. ball position designation per jesd 95-1, spp-010. 4. e represents the solder ball grid pitch. 5. symbol "md" is the ball matrix size in the "d" direction. symbol "me" is the ball matrix size in the "e" direction. n is the number of populted solder ball positions for matrix size md x me. 6 dimension "b" is measured at the maximum ball diameter in a plane parallel to datum c. 7 sd and se are measured with respect to datums a and b and define the position of the center solder ball in the outer row. when there is an odd number of solder balls in the outer row sd or se = 0.000. when there is an even number of solder balls in the outer row, sd or se = e/2 8. "+" indicates the theoretical center of depopulated balls. 9. n/a 10 a1 corner to be identified by chamfer, laser or ink mark, metallized mark indentation or other means. e1 7 se a d1 ed dc e f g h 8 7 6 4 3 2 1 ee 5 b pin a1 corner 7 sd bottom view c 0.08 0.20 c a e b c 0.15 (2x) c d c 0.15 (2x) index mark 10 6 b top view side view corner 56x a1 a2 a 0.15 m m c c ab 0.08 pin a1
16 s71pl-j based mcps s71pl-j_00_b6 february 17, 2010 data sheet tsc056?56-ball fine-pitch ball grid array (fbga) 9 x 7 mm package 3427 \ 16-038.22 package tsc 056 jedec n/a d x e 9.00 mm x 7.00 mm package symbol min nom max note a --- --- 1.20 profile a1 0.17 --- --- ball height a2 0.81 --- 0.97 body thickness d 9.00 bsc. body size e 7.00 bsc. body size d1 5.60 bsc. matrix footprint e1 5.60 bsc. matrix footprint md 8 matrix size d direction me 8 matrix size e direction n 56 ball count b 0.35 0.40 0.45 ball diameter ee 0.80 bsc. ball pitch ed 0.80 bsc ball pitch sd / se 0.40 bsc. solder ball placement a1,a8,d4,d5,e4,e5,h1,h8 depopulated solder balls notes: 1. dimensioning and tolerancing methods per asme y14.5m-1994. 2. all dimensions are in millimeters. 3. ball position designation per jesd 95-1, spp-010. 4. e represents the solder ball grid pitch. 5. symbol "md" is the ball matrix size in the "d" direction. symbol "me" is the ball matrix size in the "e" direction. n is the number of populted solder ball positions for matrix size md x me. 6 dimension "b" is measured at the maximum ball diameter in a plane parallel to datum c. 7 sd and se are measured with respect to datums a and b and define the position of the center solder ball in the outer row. when there is an odd number of solder balls in the outer row sd or se = 0.000. when there is an even number of solder balls in the outer row, sd or se = e/2 8. "+" indicates the theoretical center of depopulated balls. 9. n/a 10 a1 corner to be identified by chamfer, laser or ink mark, metallized mark indentation or other means. e1 7 se a d1 ed dc e f g h 8 7 6 4 3 2 1 ee 5 b pin a1 corner 7 sd bottom view c 0.08 0.20 c a e b c 0.15 (2x) c d c 0.15 (2x) index mark 10 6 b top view side view corner 56x a1 a2 a 0.15 m m c c ab 0.08 pin a1
february 17, 2010 s71pl-j_00_b6 s71pl-j based mcps 17 data sheet tla064?64-ball fine-pitch ball grid array (fbga) 8 x 11.6 mm package 3352 \ 16-038.22a package tla 064 jedec n/a d x e 11.60 mm x 8.00 mm package symbol min nom max note a --- --- 1.20 profile a1 0.17 --- --- ball height a2 0.81 --- 0.97 body thickness d 11.60 bsc. body size e 8.00 bsc. body size d1 8.80 bsc. matrix footprint e1 7.20 bsc. matrix footprint md 12 matrix size d direction me 10 matrix size e direction n 64 ball count b 0.35 0.40 0.45 ball diameter ee 0.80 bsc. ball pitch ed 0.80 bsc ball pitch sd / se 0.40 bsc. solder ball placement a2,a3,a4,a5,a6,a7,a8,a9 depopulated solder balls b1,b2,b3,b4,b7,b8,b9,b10 c1,c2,c9,c10,d1,d10,e1,e10, f1,f5,f6,f10,g1,g5,g6,g10 h1,h10,j1,j10,k1,k2,k9,k10 l1,l2,l3,l4,l7,l8,l9,l10 m2,m3,m4,m5,m6,m7,m8,m9 notes: 1. dimensioning and tolerancing methods per asme y14.5m-1994. 2. all dimensions are in millimeters. 3. ball position designation per jesd 95-1, spp-010. 4. e represents the solder ball grid pitch. 5. symbol "md" is the ball matrix size in the "d" direction. symbol "me" is the ball matrix size in the "e" direction. n is the number of populted solder ball positions for matrix size md x me. 6 dimension "b" is measured at the maximum ball diameter in a plane parallel to datum c. 7 sd and se are measured with respect to datums a and b and define the position of the center solder ball in the outer row. when there is an odd number of solder balls in the outer row sd or se = 0.000. when there is an even number of solder balls in the outer row, sd or se = e/2 8. "+" indicates the theoretical center of depopulated balls. 9. n/a 10 a1 corner to be identified by chamfer, laser or ink mark, metallized mark indentation or other means. c 0.20 c 0.08 c b 64x 6 0.08 m c 0.15 m c a b a2 a a1 side view l m ed corner e1 7 se d1 a b dc e f hg 10 8 9 7 5 6 4 2 3 j k 1 ee sd bottom view pin a1 7 10 index mark c 0.15 (2x) (2x) c 0.15 b a d e pin a1 top view corner
18 s71pl-j based mcps s71pl-j_00_b6 february 17, 2010 data sheet tsb064?64-ball fine-pitch ball grid array (fbga) 8 x 11.6 mm package 3351 \ 16-038.22a package tsb 064 jedec n/a d x e 11.60 mm x 8.00 mm package symbol min nom max note a --- --- 1.20 profile a1 017 --- --- ball height a2 0.81 --- 0.97 body thickness d 11.60 bsc. body size e 8.00 bsc. body size d1 8.80 bsc. matrix footprint e1 7.20 bsc. matrix footprint md 12 matrix size d direction me 10 matrix size e direction n 64 ball count b 0.35 0.40 0.45 ball diameter ee 0.80 bsc. ball pitch ed 0.80 bsc ball pitch sd / se 0.40 bsc. solder ball placement a2,a3,a4,a5,a6,a7,a8,a9 depopulated solder balls b1,b2,b3,b4,b7,b8,b9,b10 c1,c2,c9,c10,d1,d10,e1,e10 f1,f5,f6,f10,g1,g5,g6,g10 h1,h10,j1,j10,k1,k2,k9,k10 l1,l2,l3,l4,l7,l8,l9,l10 m2,m3,m4,m5,m6,m7,m8,m9 notes: 1. dimensioning and tolerancing methods per asme y14.5m-1994. 2. all dimensions are in millimeters. 3. ball position designation per jesd 95-1, spp-010. 4. e represents the solder ball grid pitch. 5. symbol "md" is the ball matrix size in the "d" direction. symbol "me" is the ball matrix size in the "e" direction. n is the number of populted solder ball positions for matrix size md x me. 6 dimension "b" is measured at the maximum ball diameter in a plane parallel to datum c. 7 sd and se are measured with respect to datums a and b and define the position of the center solder ball in the outer row. when there is an odd number of solder balls in the outer row sd or se = 0.000. when there is an even number of solder balls in the outer row, sd or se = e/2 8. "+" indicates the theoretical center of depopulated balls. 9. n/a 10 a1 corner to be identified by chamfer, laser or ink mark, metallized mark indentation or other means. c c 0.08 a1 b 64x 0.15 m c a b 0.08 m c 6 side view 7 se e1 corner pin a1 a c db d1 a 10 ed 9 8 6 5 3 ee 2 4 7 e d 0.15 c (2x) gfe k jh sd 7 m l 1 c c 0.15 b (2x) 0.20 10 pin a1 corner index mark a2 a top view bottom view
february 17, 2010 s71pl-j_00_b6 s71pl-j based mcps 19 data sheet fta084?84-ball fine-pitch ball grid array (fbga) 8 x 11.6 mm package 3388 \ 16-038.21a package fta 084 jedec n/a d x e 11.60 mm x 8.00 mm note package symbol min nom max a --- --- 1.40 profile a1 0.17 --- --- ball height a2 1.02 --- 1.17 body thickness d 11.60 bsc. body size e 8.00 bsc. body size d1 8.80 bsc. matrix footprint e1 7.20 bsc. matrix footprint md 12 matrix size d direction me 10 matrix size e direction n 84 ball count b 0.35 0.40 0.45 ball diameter ee 0.80 bsc. ball pitch ed 0.80 bsc ball pitch sd / se 0.40 bsc. solder ball placement a2,a3,a4,a5,a6,a7,a8,a9 depopulated solder balls b1,b10,c1,c10,d1,d10,e1,e10 f1,f10,g1,g10,h1,h10 j1,j10,k1,k10,l1,l10 m2,m3,m4,m5,m6,m7,m8,m9 notes: 1. dimensioning and tolerancing methods per asme y14.5m-1994. 2. all dimensions are in millimeters. 3. ball position designation per jesd 95-1, spp-010. 4. e represents the solder ball grid pitch. 5. symbol "md" is the ball matrix size in the "d" direction. symbol "me" is the ball matrix size in the "e" direction. n is the number of populted solder ball positions for matrix size md x me. 6 dimension "b" is measured at the maximum ball diameter in a plane parallel to datum c. 7 sd and se are measured with respect to datums a and b and define the position of the center solder ball in the outer row. when there is an odd number of solder balls in the outer row sd or se = 0.000. when there is an even number of solder balls in the outer row, sd or se = e/2 8. "+" indicates the theoretical center of depopulated balls. 9. n/a 10 a1 corner to be identified by chamfer, laser or ink mark, metallized mark indentation or other means. (2x) c 0.08 0.20 c c 6 b side view 84x a1 a2 a 0.15 m c mc ab 0.08 bottom view ml e1 7 se a d1 ed dc e f g h j k 10 8 9 7 6 4 3 2 1 ee 5 b pin a1 corner 7 sd a e b c 0.15 d c 0.15 (2x) index mark 10 top view corner pin a1
20 s71pl-j based mcps s71pl-j_00_b6 february 17, 2010 data sheet 8. revision history section description revision a (may 3, 2004) initial release revision a1 (may 6, 2004) features corrected the high performance access times. connection diagrams added reference points on all diagrams. ordering information corrected package types. corrected the description of product family to page mode flash memory. revision a2 (may 11, 2004) general description corrected the tables to reflect accurate device configurations. revision a3 (june 16, 2004) ordering information corrected the valid combinations ta bles to reflect accurate device configurations. revision a4 (july 16, 2004) global global change of fasl to spansion. global change to remove space between m and mb callouts. 32 mb flash memory replaced ?s71pl032j08-07? with ?s71pl032j08-0b?. replaced ?s71pl032ja0? with ?s71pl032ja0-07?. replaced ?s71pl032ja0-08? with ?s71pl032ja0-0f?. added row with the following content: s71pl032ja0-08; 65; 16mb psram; 70; psram3; tlc056. 64 mb flash memory replaced ?s71pl064j08-0k? with ?s71pl064j08-0b?. replaced ?s71pl064j08-0p? with ?s71pl064j08-0u?. deleted ?s71pl064j80-05? row. replaced ?s71pl064ja0-07? with ?s71pl064ja0-0k?. replaced ?s71pl064ja0-0z? with added row with the following content:s71pl064jb 0-07; 65; 32m psram; 70; psram 1; tlc056. 128 mb flash memory added row with the following content: s71pl127 jb0-9; 65; 32m psram; 70; psram; tla064. replaced ?s71pl127jb0-97? with ?s71pl127jb0-9z?. added row with the following content: s71pl127 jc0-97; 65; 64m psram; 70; psram1; tla064. replaced ?s71pl127jc0-9p? with ?s71pl127jc0-9z?. in the s71pl254jb0-tb row changed psra m type from ?psram3? to ?psram2?. 256 mb flash memory added row with the following content: s71pl254 jb0-tb; 65; 32m psram; 70; psram3; fta084. added row with the following content: s71pl254 jc0-tb; 65; 64m psram; 70; psram2; fta084. connection diagrams updated pins d8, d9, and l5. added notes 2 and 3 to drawing. updated pins d8 and d9. added note 2 to drawing. s71pl032j valid combinations changed s71pl032j08 (p)sram type access time (n s) from ?sram1? to ?sram2? (4 changes made in table). changed s71pl032ja0 (p)sram type access time (n s) from ?sram3 / 70? to psram3 /70?. deleted all cells with the following collaborated text: ?baw,bfw, bai. bfi? . merged previous place holder with cell above. s71pl064j valid combinations in (p)sram type/access time (ns) changed al l instances of ?stet? to ?psram1/70?. in package modifier/model number changed all instances of ?stet? to ?07?. added row to baw package and temperature secti ons with the following content: s71pl064jb0; 07; 65 (previously inclusive); psram1/70. s71pl127j valid combinations changed the s71pl127ja0 package modifier/model number from ?9z? to ?9p? (4 instances). added 4 rows with the following content: s71pl127jc0; 97; psram1/70. s71pl254j valid combinations added 4 rows with the following content: s71pl254jc0; tb; psram2/70. added 4 rows with the following content: s71pl254jb0; tb; psram2/70.
february 17, 2010 s71pl-j_00_b6 s71pl-j based mcps 21 data sheet s71pl-j based mcps added 254m to megabit indicator. added 16 to cmos indicator revision a5 (september 14, 2004) product selector guide updated the 128mb flash memory table. valid combinations table updated the s71pl127j valid combinations table. revision a6 (november 22, 2004) product selector guide updated the 32mb and 64mb tables. valid combinations table updated the 32mb and 64mb combinations. physical dimensions added the tsb064 package. revision a7 (february 8, 2005) psram type 7 updated all information in this section revision a8 (april 6, 2005) s29pl-j flash updated all information in this section revision a9 (may 12, 2005) global added the s71pl064j0a option to cover the inclusion of the 16m sram revision a10 (june 22, 2005) global removed 127/16 and 254/32 psram and updated opn for 64/16sram revision a11 (july 29, 2005) psram type 7 updated this module revision b (september 29, 2005) s29pl-j flash updated this module sram type 1 updated this module revision b1 (october 25, 2005) psram type 5 added this module revision b2 (january 25, 2006) global added notices for devices not recommended for new designs modified the product selection guide modified the s71pl032j, s71pl064j, s 71pl127jvalid combinations tables revision b3 (march 17, 2006) global modified the stucture of the document. relat ed data sheets are referenced rather than be embedded. added data sheet reference table to that effect. added the sram type 4 option added the 8mb psram type 3 option revision b4 (december 22, 2006) global added the s71pl064j80-07 for psram type 4 removed the s71pl064j08-0b revision b5 (july 17, 2007) global updated product status for all listed products ordering information revised ordering information for s71pl032ja0 and s71pl064jb0 mcps revision b6 (february 17, 2010) ordering information added q description under package modifier section description
22 s71pl-j based mcps s71pl-j_00_b6 february 17, 2010 data sheet colophon the products described in this document are designed, developed and manufactured as contemplated for general use, including wit hout limitation, ordinary industrial use, genera l office use, personal use, and household use, but are not designed, developed and m anufactured as contemplated (1) for any use that includes fatal risks or dangers t hat, unless extremely high safety is secured, could have a s erious effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic contro l, mass transport control, medical life support system, missile launch control in we apon system), or (2) for any use where chance of failure is intole rable (i.e., submersible repeater and artifi cial satellite). please note that spansion will not be liable to you and/or any third party for any claims or damages arising in connection with abo ve-mentioned uses of the products. any semic onductor devices have an inherent chance of failure. you must protect agains t injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. if any products described in this document r epresent goods or technologies s ubject to certain restriction s on export under the foreign exchange and foreign trade law of japan, the us export ad ministration regulations or the applicable laws of any oth er country, the prior authorization by the respective government entity will be required for export of those products. trademarks and notice the contents of this document are subjec t to change without notice. this document ma y contain information on a spansion product under development by spansion. spansion reserves the right to change or discontinue work on any product without notice. the informati on in this document is provided as is without warran ty or guarantee of any kind as to its accuracy, completeness, operability, fitness for particular purpose, merchantability, non-infringement of third-party rights, or any other warranty, express, implied, or statutory. spansion assume s no liability for any damages of any kind arising out of the use of the information in this document. copyright ? 2004-2010 spansion inc. all rights reserved. spansion ? , the spansion logo, mirrorbit ? , mirrorbit ? eclipse?, ornand?, ecoram? and combinations thereof, are trademar ks and registered trademarks of spansion llc in the united states and other count ries. other names used are for informati onal purposes only and may be trademarks of their respective owners.

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